1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically, to semiconductor memory devices whose bit lines can be partially operated. Description of the Prior Art
Semiconductor memory devices have been remarkably developed, and various technologies have been proposed to reduce power consumption of random access memories (RAM).
FIG. 1 is a block diagram showing an example of a conventional DRAM structure. Referring to the figure, a memory cell array 101 comprises a plurality of word lines and a plurality of bit lines intersecting with each other, with memory cells arranged at respective intersections between the word lines and the bit lines. By selecting one word line by means of a X address buffer decoder 102 and by selecting one bit line by means of a Y address buffer decoder 103, a memory cell at the intersection can be selected. Data is written to the selected memory cell and the data stored in the memory cell is read therefrom. The writing/reading of data is carried out by a reading/writing control signal (R/W) provided to a R/W control circuit 104. In writing data, an input data (D.sub.in) is inputted to the selected memory cell through the R/W control circuit 104. In data reading, the data stored in the selected memory cell is detected and amplified by a sense amplifier 105 to be externally outputted as an output data (Dout) through a data output buffer 106.
FIG. 2 is a schematic diagram showing a conventional bit line pair included in the memory cell array of FIG. 1, which is disclosed in, for example, "A 288K CMOS Pseudostatic RAM" IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, pp 619-623, October 1984.
Referring to the figure, a plurality of word lines (only word lines WL.sub.1, WL.sub.2, WL.sub.5, and WL.sub.6 are shown) are arranged to intersect the bit line pair BL and BL, and memory cells MC (only memory cells MC.sub.1, MC.sub.2, MC.sub.5 and MC.sub.6 are shown) are provided at the intersections of respective the bit lines BL and BL and the word lines WL. Since each memory cell has the same structure, description will be given only of the memory cell MC.sub.1 at the intersection with the word line WL.sub.1. The memory cell MC.sub.1 comprises a transfer transistor Q.sub.S1 and a memory capacitor C.sub.1. The transistor Q.sub.S1 is connected between the memory capacitor C.sub.1 and the bit line BL or BL with the gate connected to the word line WL.sub.1.
An N type sense amplifier NSA and a P type sense amplifier PSA constituting the sense amplifier 105 are connected to the bit line pair BL, BL. The N type sense amplifier NS comprises N channel MOS transistors Q1 and Q2. The transistor Q1 is connected between the bit line BL and a node N1 with the gate connected to the bit line BL. The transistor Q2 is connected between the bit line BL and the node N1 with the gate connected to the bit line BL. The node N1 is coupled to the ground potential through an N channel MOS transistor Q3 with a sense amplifier activating signal S.sub.N applied to the gate of the transistor Q3. The P type sense amplifier PSA comprises P channel MOS transistors Q4 and Q5. The transistor Q4 is connected between the bit line BL and a node N2 with the gate connected to the bit line BL. The transistor Q5 is connected between the bit line BL and the node N2 with the gate connected to the bit line BL. The node N2 is coupled to a supply potential V.sub.cc through a P channel MOS transistor Q6 with a sense amplifier activating signal S.sub.p applied to the gate of the transistor Q6. An N channel MOS transistor Q7 for equalization is connected between the bit line pair BL and BL, with an equalizing signal BLEQ applied to the gate thereof.
FIG. 3 is a diagram of waveforms showing the operation of FIG. 2. The operation of the circuit shown in FIG. 2 will be described with reference to the diagram of waveforms. The operation when the word line WL.sub.1 is selected is shown in this example. When a row address strobe signal RAS is at the "H" level, that is, in an off time period, the sense amplifier activating signal S.sub.N becomes "H" level and the sense amplifier activating signal S.sub.P becomes "L" level, so that the sense amplifiers NSA and PSA are in the active state. Consequently, the potential of one of the bit lines BL and BL is held at the "H" level, namely, V.sub.cc potential, and the potential of the other one is held at the "L" level, namely, the ground potential.
When the row address strobe signal RAS is at the "L" level, that is, in the active period, first, the sense amplifier activating signal S.sub.N is set at the "L" level and the sense amplifier activating signal S.sub.P is set at the "H" level to bring the sense amplifiers NSA and PSA to inactive state, and thereafter the equalizing signal BLEQ is once set at the "H" level so as to short-circuit the bit line pair BL and BL. Consequently, the potential of the bit line BL and that of the bit line BL are both brought to an intermediate potential (precharge potential), that is, 1/2 V.sub.cc, which is an intermediate potential between the "H" level and the "L" level. The equalizing signal BLEQ is reset at the "L" and thereafter, a word line driving signal WL.sub.1 rises to the "H" level. Consequently, the information in the memory cell MC.sub.1 connected to the selected word line WL.sub.1 is read to the corresponding bit line BL, and the potential of the bit line BL slightly increases or decreases in accordance with the information of the memory cell MC.sub.1. On this occasion, the potential of the bit line BL to which the selected memory cell MC.sub.1 is not connected is kept at the above described precharge potential. When the sense amplifier activating signal S.sub.N is set at the "H" level and the sense amplifier activating signal SP is set at the "L" level to activate the sense amplifiers NSA and PSA, the potential difference between the bit lines BL and BL is amplified. The amplifying operation will be more specifically described with reference to a case in which the potential of the bit line BL is higher than that of the bit line BL. The transistor Q1 is turned on by the potential of the bit line BL, and the bit line BL is connected to the ground voltage through the node N1 and the transistor Q3. The transistor Q5 turns on by the bit line BL which has become the ground potential, and the bit line BL is connected to the power supply voltage through the transistor Q5, the node N2 and the transistor Q6. Consequently, the bit line BL or BL which has the higher potential (in this case the bit line BL) is fixed at the "H" level, and the bit line having the lower potential (in this case the bit line BL) is fixed at the "L" level. The refresh and reading operation of the memory cell MC.sub.1 is carried out in this manner. Thereafter, when the row address strobe signal RAS rises to the "H" level to terminate the active period, a word line driving signal falls to the "L" level. As a result, the transistor QS.sub.1 of the memory cell MC.sub.1 connected to the selected word line WL.sub.1 is turned off. However, the sense amplifiers NSA and PSA are kept active until the start of the next active period. When the row address strobe signal RAS becomes "L" level to start the active period, the above described operation is repeated again.
Since the conventional semiconductor dynamic RAM is structured as described above, the charges of one bit line which is at 1/2 V.sub.cc are discharged every time the sense amplifier is activated. Namely, in the above example, the bit line BL having the charges of 1/2 V.sub.cc is connected to the ground power supply through the transistor Q2, the node N1 and the transistor Q3, so that the charges held by the bit line are lost. Therefore, much power is consumed in refreshing and reading.